This invention relates to a multiple circuit board package employing solder balls and fabrication method and apparatus, particularly for the fabrication of high density, multi-layered electronic circuit packages, and more particularly second tier packages of a plurality of multi-layer circuit boards.
In the electronics industry, particularly in the prototyping of large scale integrated circuits, there is a need for interconnecting electronic devices, such as integrated circuit packages, packaged integrated circuits, and discrete devices, in highly dense packaging so as to reduce signal path lengths and overall size. It has long been a practice to fabricate a multi-layered circuit board having layers of distinct circuit patterns separated by insulating material such as fiberglass or ceramic and interconnected by "vias" through the board, that is, holes drilled through the board and plated with metal. The electronic devices are mounted on a surface of the board and connected to a circuit pattern thereon at pads, which are usually larger than the rest of the pattern to accept the leads or contacts of the electronic device. Multi-layered circuit boards are shown, for example, in DiStefano et al. U.S. Pat. No. 5,376,764, and Swamy U.S. Pat. No. 5,576,519, herein incorporated by reference in its entirety.
There is a practical limit to the number of layers that can be provided in a multi-layered circuit board, and a concomitant limit to the number of interconnections that can be made between electronic devices with such circuit boards. This is because, as a board becomes thicker with additional layers of circuit patterns, it becomes increasingly difficult to place vias in the board and the board fabrication yield drops. Vias are placed by drilling holes in the multi-layered board. The deeper the via, the more drill bit wander that is produced when holes are drilled, which produces a non uniform and usually expanding hole progressively through the via. This increases the hole size tolerance, thereby reducing the possible circuit density, and makes plating the inside of the vias more difficult. Indeed, surface tension of the plating metal makes it very difficult to uniformly plate the interior of a via having a high aspect ratio, that is, the ratio of the via depth to the diameter of the via opening. Expensive precision drilling machinery is required and, even then, one must accept a relatively low likelihood of producing a useful board.
The aforementioned problems with multi-layered circuit boards are particularly disadvantageous in constructing prototypes of large scale circuits. By their nature, prototypes are experimental and usually subject to change. As signal path lengths are often a significant factor in circuit operation, it is usually desirable to make the prototype board as compact as possible. Fabricating prototypes with multi-layered circuit board technology alone is both expensive, due to the inherently costly process, the need to redo the entire board to make a change and low yield, and limited in its ability to minimize signal path lengths.
Combinations of multi-layered circuit boards have previously been proposed for overcoming the aforementioned problem of fabricating multi-layered boards with many layers in Swamy U.S. Pat. Nos. 5,456,004 and 5,576,519. These patents propose interconnecting a plurality of multi-layer circuit boards with interconnect sheets having solder placed in sheet vias at interconnect locations. However, this requires an additional interconnect sheet fabrication process.
Combinations of multi-layered circuit boards have also been proposed for achieving three dimensional circuit packaging in Davidson et al. U.S. Pat. No. 5,495,397. However, this requires an additional circuit board for mounting and maintaining the spacing of the multi-level circuit boards.
Small scale multi-layered circuit boards have also been used to package individual electronic circuit devices for mounting on another, larger scale multi-level circuit board, sometimes using ball grid array technology ("solder balls"), as shown, for example, in Nguyen U.S. Pat. No. 5,477,933. While this straightforward combination of multi-layered circuit boards and solder balls is effective on a small scale, that is, with relatively few interconnections, it cannot produce high yields and reliable packages on a large scale. This is because, when large scale multi-layered circuit boards are simply joined together using solder balls, the variations in spacing over the surface area of the boards often cause many of the connections to spread out and short, yet leaves open many locations where a connection was to be made.
Solder balls have typically been used to mount chip carriers to circuit boards, as shown for example in Wilson et al. U.S. Pat. No. 5,572,405 and Acocella et al. U.S. Pat. No. 5,591,941. Often, the solder balls used are of the type having a high melting point core, typically made of copper, and a low melting point exterior made of solder. Use of solder balls having high melting point cores increases the likelihood that, when the solder is melted to wet the circuit pads, a connection will be made without causing so much solder to flow as to produce a short. However, even the use of solder balls with high melting point cores does not overcome the high probability of opens in attempting to make large scale packages of multi-layered circuit boards. Also, where there are many interconnections between boards, misalignments of the boards often cause movement of the solder balls when the boards are placed together, leading to failed connections.
Therefore, there is a need for an improved multiple circuit board package employing solder balls and a fabrication method and apparatus.